Semiconductor device, and method for manufacturing the same
US6267479A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1999 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Feb 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0191
Abstract
There is described a semiconductor device which includes in a single chip a high withstanding voltage transistor and a low withstanding voltage transistor and which imparts each of the transistors with a relevant threshold voltage and a characteristic suitable for retarding hot carriers. Specifically, an impurity profile is imparted to a lightly-doped extension (LDDEX) region formed across a channel region of a low withstanding voltage NMOS transistor, and a different impurity profile is imparted to an LDDEX region formed across a channel region of a high withstanding voltage NMOS transistor. These impurity profiles bring the threshold voltages of the MOS transistors to individual relevant voltages and retard hot carriers in the individual MOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.