Trench isolation method for semiconductor integrated circuit
US6268265A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1999 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Jul 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trench isolation method is provided for fabricating a semiconductor integrated circuit without a recessed groove that exposes the upper corner of the trench. A mask pattern is formed that exposes a predetermined area. A trench is etched through the mask pattern. Then a thermal oxide film is formed on the side walls and the bottom of the trench. A flowable oxide is then filled in the trench overflowing onto the mask pattern, and formed into a pattern. Then a surface of the flowable oxide film is etched until the mask pattern is exposed, thereby forming a flowable oxide film pattern. Then the exposed mask pattern is removed by a wet etchant, which also etches the flowable oxide film pattern, and thus forms a recessed groove. Then thermal annealing is performed, which eliminates the grooves, and forms an isolation film covering the upper corner of the trench. The thermal oxide film prevents impurities of the flowing oxide from diffusing into the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.