Silicon packaging with through wafer interconnects
US6268660A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1999 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Mar 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package for integrated circuit chips. The package contains a silicon substrate having a top surface and a bottom surface. The package also contains a first means for electrically connecting the integrated circuits to the substrate attached to the top surface of the substrate. A multilevel wiring is located at the top surface and is coupled to the first connecting means and serves as a communication link among a plurality of the first connecting means to enable multi-chip processing. A via containing means for coupling the multilevel wiring at the top surface to the bottom surface runs through the substrate from the bottom surface to the top surface. A second means is also present for connecting the coupling means at the bottom surface of the substrate with external components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.