Block symmetrization in a field programmable gate array
US6268743A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 6, 2000 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Mar 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16.times.16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16.times.16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16.times.16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the four clusters includes first and second LUT3s, a LUT2, and a DFF . Each of the LUT3s have first, second, and third inputs and a single output. Each of the LUT2s have first and second inputs and a single output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are mul…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.