Duty cycle optimized prescaler
US6268751A · kind A · utility
2Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1999 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Dec 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Duty cycle optimized prescaler (10) optimizes the clock duty cycle as close as possible to fifty percent. This is achieved by employing two count by two counters (11,12), one (12)to count negative edges of the clock pulse, and one (11)to count positive edges of the clock pulse. Each counter (11,12) output is connected to a comparator (14,15) which compares each counter output (11,12)to a prescaler setting (13). The comparators (14,15) outputs are input to an OR gate (16), the output of which, when, a logic 1, resets the counters(11,12) and toggles a flip-flop circuit (17) providing a clock output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.