2.5V, 30-100 MHz 7th order equiripple delay continuous-time filter and variable gain amplifier
US6268765A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1998 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Dec 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/0466
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit is designed with a first transconductor circuit (903) with a first input terminal (901) coupled to receive a voltage signal, a second input terminal (1017) coupled to receive a control signal and an output terminal. The first transconductor circuit has a gain responsive to the control signal. A first integrator circuit (905) has an input terminal coupled to the first transconductor circuit output terminal and has an output terminal. A second transconductor circuit (909) has an input terminal coupled to the first integrator circuit output terminal and an output terminal. A second integrator circuit (911) has an input terminal coupled to the second transconductor circuit output terminal and has an output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.