Priority encoder/read only memory (ROM) combination
US6268807A · kind A · utility
8Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2000 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Feb 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a priority encoder (PE)/read-only-memory (ROM) combination circuit (200) includes detect circuits (206-xy) and passgate circuits (208-xy) arranged into rows (202-x) and columns (202-y). Detect circuits (206-xy) of the same column can be activated by a corresponding input signal (M0 to M7). When a detect circuit (206-xy) of a column (202-y) is activated, the passgates (208-xy) of the same column are disabled, preventing any lower priority active input signals (M0 to M7) from propagating further into the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.