Digital differential analyzer data synchronizer
US6269136A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1998 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Feb 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0012
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital differential analyzer data synchronizer receives data at a first clock rate and synchronizes the data to a second clock rate. The two clock rates are related by a ratio of two integers, but have a variable phase relationship. The synchronizer places incoming data into a series of registers at the first clock rate. A digital differential analyzer functions to generate a synchronization signal having a frequency proportional to a ratio of the first clock rate and the second clock rate. A multiplexer is utilized for sequentially reading the plurality of registers at a rate corresponding to the frequency of the synchronization signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.