Apparatus and method for performing rounding and addition in parallel in floating point multiplier
US6269385A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1998 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Jul 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49957
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and a method for performing rounding and addition in parallel in a floating point multiplier are disclosed, in which operation time and the size of a chip can be reduced. The apparatus includes an adder having an n bit half adder and an 1 bit full adder to add high n+1 bit from carry C and sum S of 2n bit and 1 bit of predictor, a C.sup.in.sub.n-2 generator for generating carry C.sup.in.sub.n-2 for addition of low n-2 bit to carry C and sum S of 2n bit, a predictor for providing 0 or 1 to the full adder when generating the added carry C of n bit and sum S of n+1 bit, a carry select adder for adding 0 or 1 to high n bit value of carry and sum added through the adder to output its result values i0 and i1, a selector for outputting a control signal of 0 or 1 to select a value obtained by addition and rounding from two output values of the carry select adder, a multiplexer for multiplexing the results of i0 and i1 from one of a round-to-nearest mode, a round-to-zero mode, and a round-to-infinity mode in response to the control signal of the selector, and a q.sup.NS.sub.0 logic circuit for generating the least significant bit LSB for a round value during no shift (NS). The …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.