Split I/O circuit for performance optimization of digital circuits
US6269468A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1999 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Mar 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic circuit device and circuit design methodology includes a "split-book" logic circuit design having different active device sizes with outputs for connections to both critical and non-critical digital circuit paths. By using "split" book designs with separate input and output stages, better silicon utilization, power optimization, and performance results. This is because each split book is designed with multiple output buffers that may be configured to optimally drive critical and non-critical paths. During the power/performance optimization phase of the design, timing critical paths of the design are first identified, with each path being optimized on its own basis. First the input stage of the strand may be improved with a stronger drive on the input port of the book. Only the input port that has been linked to a critical path is updated. The other input pins are left at their default setting. Then, the output buffers may then be connected together according to criticality of the path and net capacitive load they are driving. Different split book input/output circuit combinations may be attempted during the design phase until an optimal tradeoff between power optimization a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.