Method for producing filled vias in electronic components
US6270601A · kind A · utility
13Cited by
48References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1998 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Nov 2, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24157
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
The present invention relates to a process for producing filled vias which are made of two components, a first component which forms a bonding layer between the wall of the via and a second component which forms the core of the via. Preferably, the two components solidify from a melt which includes two immiscible liquids. The first liquid is capable of wetting the wall of the via and the second liquid. The resulting product is also disclosed. Preferably the first component comprises a copper oxide and the second component comprises a conductive metal such as silver or copper.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.