Process for integrating dielectric optical coatings into micro-electromechanical devices

US6271052A · kind A · utility

Assignee

• Axsun Technologies, Inc. · US

Inventors

• Michael F. Miller · Hollis, US
• Minh Le · Methuen, US
• Christopher C. Cook · Bedford, US
• Dale C. Flanders · Lexington, US

Key dates

• Filing date: Oct 19, 2000
• Grant date: Aug 7, 2001
• Expiry date: Oct 19, 2020

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B81C2201/053
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A process for fabricating an optical membrane from polycrystalline silicon comprises first forming a sacrificial layer on a handle wafer. Concavities are etched into the sacrificial layer. Polycrystalline silicon membrane layer is then formed on the sacrificial layer. The polycrystalline membrane layer is subsequently polished to achieve the predetermined membrane thickness and surface smoothness, annealed, and then patterned. Finally, the sacrificial layer is removed to release the membrane. The concavities in the sacrificial layer yield convexities in the polysilicon layer to prevent stiction adhesion to the handle wafer. During processing, a mask used to pattern the membrane layer functions to protect an highly reflecting (HR) coating for the membrane.