Method of forming multiple wells in a semiconductor integrated circuit using fewer photolithography steps
US6271105A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 1999 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | May 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a multiple well of a semiconductor device is provided. By this method, a pocket well region of a first conductivity type is formed over a predetermined first region of a semiconductor substrate of a first conductivity type, using a first photolithography process. A first deep well region of a second conductivity type is then formed under the pocket well region in a self-aligned manner. A peripheral well region of the first conductivity type is selectively formed in a predetermined second region of the semiconductor substrate apart from the pocket well region, using a second photolithography process. An ion-implantation mask covering the pocket well region and the peripheral well region of the first conductivity type is formed using a third photolithography process, and is used to form a peripheral well region of the second conductivity type and a second deep well region of the second conductivity type in a self-aligned manner under the peripheral well region of the second conductivity type, in the exposed areas of the semiconductor substrate. In this way, a triple well region is formed using only three photolithography processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.