Belowground and oversupply protection of junction isolated integrated circuits

US6271567A · kind A · utility

Assignee

• STMicroelectronics SA

Inventors

• Massimo Pozzoni · Pavia, IT
• Paolo Cordini · Pavia, IT
• Domenico Rossi · Mortara, IT
• Giorgio Pedrazzini · Pavia, IT
• Paola Galbiati · Monza, IT
• Michele Palmieri · Bitonto, IT
• Luca Bertolini · Milano, IT

Key dates

• Filing date: Jan 11, 1999
• Grant date: Aug 7, 2001
• Expiry date: Jan 11, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

In a junction isolated integrated circuit including power DMOS transistors formed in respective well regions or in an isolated epitaxial region on a substrate of opposite type of conductivity, circuits are formed in a distinct isolated region sensitive to oversupply and/or belowground effects. These effects are caused by respective power DMOS transistors coupled to the supply rail or ground. These effects are alternatively controllable by specifically shaped layout arrangements, and may be effectively protected from both effects. This is achieved by interposing between the region of sensitive circuits and the region containing the power DMOS transistors for which the alternatively implementable circuital arrangements are not formed, the region containing the power DMOS transistors coupled to the supply rail or to a ground rail for which the alternatively implementable arrangements are formed. The special interposition separates and shields the sensitive circuits from the power device whose oversupply or belowground effect is not countered by specific circuit arrangements.