Clock circuit for generating a delay
US6271702A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 1998 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Jun 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay generation circuit comprising (i) a circuit configured to generate a reference clock signal having a period, (ii) a divide circuit and (iii) an output circuit. The divide circuit may be configured to generate a first divided clock signal and a second divided clock signal in response to said reference clock signal. The output circuit may be configured to generate (i) a first output clock signal and (ii) a second output clock signal in response to (i) the first and second divided clock signals and (ii) the reference clock signal. The second output clock signal may have a delay with respect to the first output clock signal. The delay may be (i) a multiple of or (ii) a fraction of the period of the reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.