Semiconductor integrated circuit device having fuses and fuse latch circuits
US6272061A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Aug 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device has a semiconductor integrated circuit with first layout sections where fuses are laid out and second layout sections where fuse latch circuits, which correspond to the fuses, are laid out. The first layout sections are disposed in a first repetition pitch in a fuse area, while the second layout sections are laid out at a second repetition pitch smaller than the first repetition pitch in a fuse latch circuit area. A third layout section is laid out in a space caused by the difference between the first and second repetition pitches. In the third layout section, at least one of patterns which are unrepeatable in each of the second layout sections and the patterns which do not need to be repeated in each of the second layout sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.