Concurrent legacy and native code execution techniques
US6272453A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1999 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Nov 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45504
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for emulating instructions of a microprocessor ("legacy instructions") with an incompatible instruction set which provides increased throughput relative to known emulation systems. In particular, each word of legacy memory is translated into an opcode/operand field and a dual function vector/tag field. The vector field represent addresses to legacy instruction emulation routines. The tag field is indexed to table of "thunk" objects, which can be used for various purposes. Such purposes include a disabling part of the legacy software, augmenting the legacy software with native software, and gathering execution statistics without modifying the legacy software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.