System for interposing a multi-port internally cached DRAM in a control path for temporarily storing multicast start of packet data until such can be passed
US6272567A · kind A · utility
40Cited by
10References
32Claims
0Family size
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Key dates
| Filing date | Nov 24, 1998 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Nov 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new data packet cell control method and apparatus, particularly, though not exclusively, for use with I/O packet cell source and destination resource networks using shared central multi-port internally cached dynamic random access memory (AMPIC DRAM), wherein a separate control path architecture is used, also incorporating AMPIC DRAM technology, to obviate problems with data traffic congestion resulting from significant I/O resource and for bandwidth requirement increases, and doing so while enabling scaling with data path, and retaining quality of service and increased multicast functionality, as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.