Pipelined memory controller
US6272609A · kind A · utility
180Cited by
5References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 31, 1998 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Jul 31, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02T10/12
- WIPO fieldEngines, pumps, turbines
- WIPO sectorMechanical engineering
Abstract
A memory controller which has multiple stages of pipelining. A request buffer is used to hold the memory request from the processor and peripheral devices. The request buffer comprises a set of rotational registers that holds the address, the type of transfer and the count for each request. The pipeline includes a decode stage, a memory address stage, and a data transfer stage. Each stage of the pipeline has a pointer to the request buffer. As each stage completes its processing, a state machine updates the pointer for each of the stages to reference a new memory request which needs to be processed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.