Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
US6272616A · kind A · utility
273Cited by
12References
48Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1998 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Jun 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3889
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel processing architecture for a digital processor capable of alternately operating in a single threaded mode, a SIMD (single instruction, multiple data) mode and a MIMD (multiple instructions, multiple data) mode. The instruction set for the processor includes instructions for switching between modes and exchanging data between the parallel processing paths. The hardware in any instruction path or portion of an instruction path which is not being used is deactivated to save power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.