System and method for handling interrupts in a multi-processor computer
US6272618A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1999 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Mar 25, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for handling system management interrupts in a multi-processor computer is disclosed. When the computer enters system management mode, the method uses the registers of each processor to get currently executing opcode to determine what each processor was doing before the interrupt. The method may have to first translate address information to locate the actual physical location of the currently executing opcode. The registers are stored in memory and the contents of the registers can be used to determine if the current processor caused the system management interrupt. If so, then the method now knows which processor caused the interrupt and can handle the interrupt accordingly. If, however, the processor was not the one that caused the interrupt, or if another processor also caused an interrupt, the method then repeats the above steps for the next processor of the multiprocessor system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.