Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation
US6272620A · kind A · utility
14Cited by
12References
6Claims
0Family size
Assignees
Inventors
- Shumpei Kawasaki
- Eiji Sakakibara
- Kaoru Fukada
- Takanaga Yamazaki
- Yasushi Akao
- Shiro Baba
- Toshimasa Kihara
- Keiichi Kurakazu
- Takashi Tsukamoto
- Shigeki Masumura
- Yasuhiro Tawara
- Yugo Kashiwagi
- Shuya Fujita
- Katsuhiko Ishida
- Noriko Sawa
- Yoichi Asano
- Hideaki Chaki
- Tadahiko Sugawara
- Masahiro Kainaga
- Kouki Noguchi
- Mitsuru Watabe
Key dates
| Filing date | Apr 4, 2000 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Apr 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5352
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.