Synchronization and control system for an arrayed processing engine
US6272621A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2000 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Aug 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control system further includes an input header buffer (IHB) and an output header buffer (OHB), the latter comprising circuitry for receiving current transient data processed by the pipelines and for decoding control signals to determine a destination for the processed data. One destination is a feedback path that couples the OHB to the IHB and returns the processed data to the IHB for immediate loading into an available pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.