Programmable logic device having an integrated phase lock loop
US6272646A · kind A · utility
107Cited by
23References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1996 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Sep 4, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention integrates a phase lock loop (PLL) with a programmable logic device (PLD) to realize a flexible PLD with a variety of clocking options. The present invention generates multiple clock frequencies internally to a programmable logic device using a single reference clock input. The programmer can dynamically change the functionality of the programmable logic device. As a result, a "virtual hardware device" is realized. The ability to change the frequency of operation also dynamically offers a tremendous advantage to users of reconfigurable computing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.