Multilayered wiring structure and method of manufacturing the same
US6274404A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1999 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Sep 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0733
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multilayered wiring structure includes a lower wiring layer, an interlevel insulating layer, a filling layer, an upper wiring layer, and a plated layer. The lower wiring layer is formed on a lead frame through an insulating layer. The interlevel insulating layer is formed on the lower wiring layer to have a via hole at a predetermined region thereof to expose an upper portion of the lower wiring layer. The filling layer is made of a conductive material to fill the via hole. The upper wiring layer is formed on the interlevel insulating layer to have an opening above a portion where the via hole is formed. The plated layer is formed on the upper wiring layer to be connected to the filling layer. A method of manufacturing a multilayered wiring structure is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.