Semiconductor device having multilayer interconnection structure and method for manufacturing the same
US6274452A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1997 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Nov 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
After an insulating layer made of BPSG is formed on a diffusion layer, a contact hole is formed to expose the diffusion layer. Then, a first aluminum layer is formed in the contact hole. Then, first and second TEOS layers are formed. Thereafter, a thin film resistor is formed on the second TEOS layer by photo-lithography and etching treatments. In this process, the other parts are covered with the second TEOS layer to prevent being damaged. As a result, occurrence of a leak current at the diffusion layer and the like can be prevented. Further, a third TEOS layer is formed on the thin film resistor, and then a second aluminum layer is formed to be electrically connected to the thin film resistor through a contact hole by an ECR dry etching treatment. In this etching treatment, the thin film resistor is not damaged due to the third TEOS layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.