Guard ring structure with deep N well on ESD devices

US6274909A · kind A · utility

Assignee

• Etron Technology, Inc. · TW

Inventors

• Kun-Zen Chang · Hsinchu, TW
• Deng-Shun Chang
• Rong-Tai Kao · Hsinchu, TW

Key dates

• Filing date: Nov 12, 1999
• Grant date: Aug 14, 2001
• Expiry date: Nov 12, 2019

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/983

Abstract

In this invention a deep N-type wall is created surrounding an area that contains an ESD device, or circuit. The ESD device, or circuit, is connected to a chip pad and is first surrounded by a P+ guard ring. The P+ guard ring is then surrounded by the deep N-type wall to block excess current from an ESD event or voltage overshoot from reaching the internal circuitry. The deep N-type wall comprises an N+ diffusion within an N-well which is on top of a deep N-well. The height of the deep N-type wall is approximately 4 to 6 micrometers which provides a capability to absorb much of the current from an ESD event or voltage overshoot.