Circuit for reducing input voltage

US6275015A · kind A · utility

Assignee

• Robert Bosch GmbH · DE

Inventors

• Andreas Kneer · Wissen, DE
• Peter Lutz · Birkenfeld, DE

Key dates

• Filing date: Mar 8, 2000
• Grant date: Aug 14, 2001
• Expiry date: Mar 8, 2020

Classification

• Technology area (CPC G): Physics
• CPC primary: G01P3/4802
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A circuit arrangement for reducing a variable, in particular pulsed input voltage (U.sub.ein) to an operating voltage U.sub.z, U.sub.arb to be delivered to an evaluation circuit (10), in which the input voltage U.sub.ein can be reduced, in accordance with a division factor (F) made available by at least one voltage divider (R1, R3, T1, R4; R7, R8, R2), to obtain the operating voltage U.sub.z, U.sub.arb, in which the at least one voltage divider (R1, R3, T1, R4; R7, R8, R2), can be regulated in such a way that the division factor (F) can be increased with an increasing input voltage U.sub.ein and can be decreased with a decreasing input voltage U.sub.ein.