Enhanced single event upset immune latch circuit
US6275080A · kind A · utility
29Cited by
23References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2000 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Jan 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An enhanced single event upset immune CMOS latch circuit is formed of a first and a second cross-coupled invertor having isolation transistors in the path coupling the drains of the transistors in the first invertor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.