Content address memory circuit with redundant array and method for implementing the same
US6275406A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2000 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Aug 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a CAM circuit having a redundant array and method for implementing the same. The circuit includes a first CAM array, a redundant CAM array, one or more storage devices, a first encoder, and a redundant encoder. The first CAM array stores data and has a plurality of first entries. Each first entry has a plurality of first memory cells, wherein any first entry that includes one or more defective first memory cells is defective. The redundant CAM array has one or more redundant entries of redundant memory cells. Each of the one or more redundant entries has a redundant address and is associated with a defective first entry, wherein each redundant entry is configured store data for the associated first entry. The one or more storage devices associate each of the defective first entries with a redundant entry. The first encoder outputs a first search result from the first CAM array while the redundant encoder outputs a redundant search result from the redundant CAM array according to a specified algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.