Modular architecture pet decoder for ATM networks
US6275495A · kind A · utility
2Cited by
4References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1998 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Sep 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5647
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A PET decoder for an ATM network has a modular architecture including a processing unit having various memories and a processing pipeline for constructing from a block of m data of a certain number of bits, a square matrix A based on a vector D of relative points over the Galois field. The processing pipeline also decomposes by triangular factorization the square matrix A and solves the subsystem of equations by simple substitution. The decoder also includes a control unit interfacing with the ATM network, a programmable parallel processor, a random access memory and the processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.