Media access controller capable of connecting to a serial physical layer device and a media independent interface (MII) physical layer device
US6275501A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1998 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Apr 21, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network node includes a serial physical sublayer (PHY) chip, a parallel PHY chip, and a media access control (MAC) chip. The serial physical sublayer chip, includes a single bit transmit data input, a single bit receive data output, and serial PHY control signal input/output (I/O) lines. The parallel PHY chip includes a multi-bit transmit data input, a multi-bit receive data output, and parallel PHY control signal I/O lines. The MAC chip includes a multi-bit transmit data output, a multi-bit receive data input and parallel control signal I/O lines. The multi-bit transmit data output is connected to the multi-bit transmit data input. One bit of the multi-bit transmit data output is connected to the single bit transmit data input. The multi-bit receive data input is connected to the multi-bit receive data output. One bit of the multi-bit receive data input is connected to the single bit receive data output. The parallel control signal I/O lines are connected to the parallel PHY control signal I/O lines. A subset of the parallel control signal I/O lines are connected to the serial PHY control signal I/O lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.