Implementation architectures of a multi-channel MPEG video transcoder using multiple programmable processors
US6275536A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1999 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Jun 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/436
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for transcoding of digital video images using a queuing system model. Multiple transcoding processors are arranged in parallel. In a first architecture, an input bitstream of n channels is partitioned into processing units, such as slices or frames, the processing units are split into m sub-streams, and each sub-stream is processed in a corresponding branch. A separate queue is provided for each sub-stream. In a second architecture, the processing units are assigned to any available processor from a common queue. Independent processing units are processed concurrently according to the queuing system model to minimize an average processing time. In particular, processing of a reference picture (I-picture) unit and an associated predicted picture (P- or B-picture unit) unit at the same time is avoided. A further technique performs record-keeping and coordinates the transfer of the reference picture unit from its processor to the processor for the associated predicted picture unit after the reference picture unit has been processed. Embodiments with picture re-ordering and use of a priority buffer are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.