Memory access controller
US6275877A · kind A · utility
Inventor
Key dates
| Filing date | Oct 27, 1998 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Oct 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A direct memory access controller is provided which utilizes a single dedicated controller to control all or substantially all memory accesses in a computer system, both memory-to-memory accesses within the system and transfers between system memory and various system peripherals. At least portions of the controller are time shared by various channels, each channel performing data transfers in a selected direction between a system memory component and a second component which may be a peripheral, another memory component or the like. An arbiter is provided as part of the controller for determining the channel using shared resources at any given time. Where one of the peripherals is a variable length packetized data source, multiple subchannels may be provided for transfers of data for such source into system memory, each such subehannel being for transfers to buffers of different size. Efficient memory utilization is achieved by determining the size of an incoming variable length packet and having the transfer performed through the channel servicing the smallest available buffer in which incoming variable length packetized data will fit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.