Low latency data path in a cross-bar switch providing dynamically prioritized bus arbitration
US6275890A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1998 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Aug 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus ports, the slave bus ports adapted to receive a plurality of slave buses; a manner of switching for selectively coupling the plurality of master bus ports to the plurality of slave bus ports; and a manner of configuration for prioritizing access requests by the plurality of master buses to the plurality of slave buses via the switching means. The cross-bar switch of the present invention has the capability of prioritizing requests between multiple parallel high speed buses. In a preferred embodiment, this arbitration is accomplished through Configuration Registers on the cross-bar switch. The Configuration Registers are programmable through the Device Control Register bus, which allows the cross-bar switch to be dynamically programmed and changed by a processor in a larger system. The cross-bar switch of the present invention minimizes the latency between data transfers. This improves the bandwidth and throughput on the on-chip bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.