Modular and scalable system for signal and multimedia processing
US6275891A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1999 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Feb 25, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/125
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A modular, scalable system architecture that includes a data traffic master for providing high-bandwidth, shared memory connections to two or more processor units. The system architecture includes an array of memory modules coupled to an array of processor units by a traffic master. Each of the memory modules is connected to the traffic master by a data channel, and each data channel includes an address path and a data path. The data channels all share a common data path bit-width. On the other hand, the processor units are each coupled to the traffic master by data busses that have address and data path widths dictated by their design. Although the address path width of a given processor unit may be unable to span the address space of the shared memory, the processor unit can nonetheless access any memory location through the use of page pointers. Further, although the data path width of a given processor unit may be too large for a single data channel to support, several data channels may be combined to provide the required data path width. The traffic master includes a processor interface port for each processor unit, and a router. The processor interface ports convert data bus …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.