Optical reader with condensed CMOS circuitry
US6276605A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1998 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Oct 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/77
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An optical or symbol reader including CMOS circuitry preferably integrated on a single chip. A CMOS optical reader chip comprises a CMOS imaging array having a plurality of pixels each with a dedicated pixel-site circuit. Charge is accumulated at each pixel location transferred upon demand to a common bus. In a preferred embodiment, exposure time of the imaging array is controlled using a feedback loop. One or more exposure control pixels are positioned adjacent to or within the imaging array and receive light along with the imaging array. The charge of the exposure control pixel or pixels is measured against a threshold level, and the amount of time taken to reach the threshold level determines the time exposure of the pixels of the imaging array. CMOS signal processing circuitry is employed which, in combination with the exposure control circuitry, minimizes time-to-read over a large range of light levels, while performing spatially optimal filtering. Clocking cycles and control signals are time-adjusted in accordance with the varying output frequency of the imaging array so as to provide invariant frequency response by the signal processing circuitry. A multi-dimensional CMOS im…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.