Method for removal of etch residue immediately after etching a SOG layer
US6277747A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Nov 9, 1998 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Nov 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor manufacturing method is disclosed, which includes the steps of: forming an interconnect layer, which may include aluminum, on a semiconductor substrate; forming an anti-reflective coating which may comprise titanium; forming a spin on glass layer; selectively etching portions of the spin on glass layer, so that predetermined portions of the interconnect layer are exposed; and applying an EKC solution to predetermined portions of the interconnect layer that are exposed. The semiconductor manufacturing may also include the steps of forming a first tetra-ethyl-ortho-silicate layer, before the step of forming a spin on glass layer; and forming a second tetra-ethyl-ortho-silicate layer, following the step of applying an EKC solution. The EKC solution in the preferred embodiment is applied for at least about a 10 minute process time. Furthermore, the semiconductor manufacturing method may include the step of forming a second interconnect layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.