Patent · US Expired

Method for fabricating stacked vias

US6277761A · kind A · utility

11Cited by

4References

7Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Wolfgang Diewald · Fontainebleau, FR
Detlef Weber · Grünberg, DE

Key dates

Filing date	Jul 21, 2000
Grant date	Aug 21, 2001
Priority date	—
Expiry date	Jul 21, 2020

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for fabricating stacked vias for microelectronic components. The method has a first step of providing a first patterned interconnect layer on a substrate. A first insulating layer is then applied on the first interconnect layer. A first via is formed in the first insulating layer and is in contact with the first interconnect layer. A second patterned interconnect layer is applied on the first insulating layer, leaving free a region around the first via. A second insulating layer is then deposited on the second interconnect layer and on the region left free around the first via. A second via is formed in the second insulating layer in such a way that it meets the first via directly.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.