Method of making fullerene-decorated nanoparticles and their use as a low dielectric constant material for semiconductor devices
US6277766A · kind A · utility
Inventor
Key dates
| Filing date | Feb 3, 2000 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Feb 3, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/773
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention provides a process for making an insulation layer for use in microelectronic devices, whereby capacitive coupling and propagation delay in the microelectronic devices are reduced. This invention can include the formation of a stable solution of nanometer-scale particles consisting of an inorganic core 10 that is decorated with a known number of fullerene molecules 20, and including a soluble component that can act to bind the particles together into an integral structure. This solution can be applied to a microelectronic substrate, and dried to form a continuous, porous layer. Porous layers formed by the process of this invention possess a very low dielectric constant, and can be produced using equipment and techniques common and available to those skilled in the art of microelectronic fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.