P-channel MOSFET semiconductor device having a low on resistance
US6278155A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1999 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Nov 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
Abstract
In a semiconductor device having a substrate, a p-type semiconductor layer, an n-type channel well region, a p-type lightly doped source region, and a source electrode formed on the substrate in this order, a p-type heavily-doped-source region, an impurity concentration of which is higher than that of the lightly-doped source region, is formed in a surface region of the lightly-doped source region. The source electrode is formed to contact the heavily-doped source region. As a result, a punch through phenomenon between the p-type source region and the p-type semiconductor layer through the n-type channel well region can be prevented without increasing in the On resistance of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.