Parasitic current barriers
US6278186A · kind A · utility
8Cited by
13References
48Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1998 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Aug 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment a substrate 14 is patterned to have high and low conductive areas 110, 112, respectively. Metal lines 104, 108 in dielectric layer 16 pass transversely over the areas 110, 112. The areas 112 interrupt parasitic inductive current induced in the substrate 14.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.