Output buffer circuit
US6278294A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1999 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Oct 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
To prevent a through current from flowing through a pair of MOS transistors of a final stage of a push-pull buffer circuit, a reset circuit is provided which receives signals individually from two inverter gate groups of a control system and an output system disposed at the stage preceding the push-pull buffer circuit, delays the input signals, and makes a logical decision on them. Even when an input/output circuit formed by two power supply systems becomes unstable at the time of power ON-OFF operation and the signal output from a signal level converter circuit yields logic that causes a through current flow into the final stage, the reset circuit forcedly cancels this logic by feedback.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.