Semiconductor device that can have standby current reduced by ceasing supply of clock signal, and that can maintain status of internal circuit
US6278303A · kind A · utility
6Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1999 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Nov 10, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock circuit is provided including a clock supply circuit that can cease clock supply according to a control signal, a PLL circuit maintaining clock synchronization, and a dummy circuit. Synchronization of the internal clock signal is maintained by the PLL circuit and the dummy circuit even in a standby state. In returning to an active state from a standby state, an unstable clock signal arising from unstable locking of the PLL circuit will not be applied to the internal circuit. Therefore, the information in the latch circuit in the internal circuit can be maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.