Method and apparatus for D.C. offset correction in digital-to-analog converters
US6278391A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2000 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Sep 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for adaptively correcting D.C. offset errors imposed upon signals in a communication device. The present invention includes a feedback loop correction circuit and method for measuring and reducing D.C. offset errors imposed upon analog transmission signals by transmit digital-to-analog converters (DACs) and associated analog reconstruction filters. A digital feedback loop is used to remove the D.C. offset errors from the analog transmission signals prior to transmission. In the preferred embodiment, the digital feedback loop includes a pair of analog-to-digital converters, a digital D.C. offset correction circuit, and a pair of adders. The transmission signals are digitized, filtered, and digitally processed by the correction circuit to generate offset correction signals that are equal to the undesired D.C. offset error present in the transmission signals. The correction signals are added to the digital input baseband signals thereby removing the undesirable D.C. offset errors from the transmission signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.