Signal processing circuit and method of operation
US6278394A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 21, 1999 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Sep 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/304
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital or digital-to-analog system contains a converter (706). The converter is supplied with a clock signal (CLK1) at a frequency fs derived from a crystal of a frequency fs/N. The frequency fs is derived from the fs/N crystal frequency by using an edge-triggered clock multiplier 705 which multiplies the crystal frequency by the factor N. The result is a low-cost clock solution that incorporates clock jitter around a localized frequency of fs/N. Sigma delta processing circuitry (702) is then used to place a null (e.g., low gain area) in the quantization noise at the same frequency where clock jitter noise is high in order to cancel the adverse cumulative effects of these two types of noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.