Ferroelectric memory device with a high-speed read circuit
US6278630A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 1998 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Dec 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory device includes a plurality of sets of bit lines which are connected to differential sense amplifiers and to a plurality of memory cells. Each memory cell contains one ferroelectric capacitor and one transistor, with a first electrode of the ferroelectric capacitor being connected to a plate line and the second electrode of the ferroelectric capacitor being connected to the source of the transistor. The gate of the transistor is connected to a word line and the drain is connected to a bit line. The memory cells generate a reference voltage which is provided to the differential sense amplifiers as a reference voltage for comparison with an data stored in the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.