High speed video frame buffer
US6278645A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1998 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Aug 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/122
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A device for storing pixel information for displaying a graphics image on a display includes a frame buffer and a processor. The information includes an intensity value and a value associated with each of a plurality of additional planes for each pixel. The frame buffer memory has a series of consecutive addresses for storing information to be output to the display. The frame buffer may be subdivided into a plurality of blocks, where each block corresponds to a region of the display having a plurality of contiguous pixels. The processor places the pixel information within the frame buffer memory so that in a given block there are placed at a first collection of consecutive addresses the intensity values for each of the pixels in the block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.