Bit synchronization circuit
US6278755A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2000 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | May 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0338
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bit synchronization circuit extracts the central phase of an eye opening irrespective of a jitter distribution of input data to maintain an optimum timing adjustment margin. The bit synchronization circuit has a data edge detector for comparing the phases of an edge of the input data and m-phase clock signals divided from a reference clock. Data edge phase information from the data edge detector is accumulated by a phase accumulation register, which stores the jitter distribution of the input data as accumulated phase information. Based on the accumulated phase information, an eye center phase calculator decodes the negative and positive ends of a jitter range as negative jitter range information and positive jitter range information, and calculates a phase control direction in relation to an extracted phase value which represents a presently selected clock phase. A correction circuit extracts the positional relationship between a present eye opening width and the extracted phase value, and clears the accumulated phase information to increase the eye opening width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.