Method of locating a failed latch in a defective shift register
US6278956A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1999 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Apr 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318525
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for locating a failing latch in a defective shift register having P latches connected in series fabricated in an integrated circuit chip. The chip is depassivated to expose its upper metalized layer, and it is in the chamber of a scanning electron microscope (SEM) having sharp voltage contrast capabilities. Clock signals are generated to properly exercise the shift register. A string of N latches, wherein 1.ltoreq.N.ltoreq.P, typically N=P/2 is first selected and the stimuli are applied to the latches to allow the output net of the last latch of the string to toggle at a frequency of about 1 Hz. The SEM beam is focused on the area which encompasses the last latch, so that, if the latch output net blinks on the SEM screen, the string under observation is deemed to be good. Then, another, more extended string is selected and the above procedure is repeated. If no blinking is detected in the newly observed string, the failing latch belongs to that string and the above procedure must also be repeated on the latches forming the string until the failing latch is identified. In a preferred embodiment, the stimuli are supplied by a stand-alone exerciser. In another embodiment, the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.